The present invention generally relates to testing integrated circuits and, more specifically, to logic built-in self-test circuitry for use in an integrated circuit with scan chains.
Digital integrated circuits are used for a diverse number of electronic applications, from simple devices such as wristwatches to the most complex computer systems. Defects in digital integrated circuits may occur.
“Stored patterns” was one of the first methods developed for testing digital integrated devices for defects. According to the stored patterns method, a value per latch of the device under test (DUT) is defined, and this data is stored in a chip tester and applied upon pattern execution. Similarly, a clock or capture sequence may be stored. After the functional clock sequence execution, the chip tester receives the measured values per latch and compares them with the expected values to determine defects in the DUT. The stored patterns method requires access of the chip tester to each latch to be tested of the DUT. With millions of latches on a chip this becomes a very time-consuming operation.
Logic built-in self-test (LBIST) has become a popular technique for on-chip testing of digital integrated circuits. LBIST offers a number of benefits targeted at the reduction of test time.
The scannable latches of the DUT may be broken into short scan chains and the major components of LBIST circuitry include a pattern generator, a signature register and an on-product test control generator.
The pattern generator is initialized with a seed and provides scan-in values to the scan chains. A clocking sequence is applied on the DUT and the signature register collects scan-out responses from the scan chains.
The chip tester only needs to store an LBIST setup that includes he seed, the loop count, and the clock sequence. As the scan-in values are generated on the DUT at higher speeds compared to the tester communication speed, the time necessary per loop is significantly reduced.
As technology advances, the number of transistors on a chip increases and the number of defects during manufacturing may increase, in particular when a new manufacturing process is introduced. Moreover, said defects may be difficult to detect. Accordingly, more thorough testing may be required, which consumes more time and augments the test time.